1. Field of the Invention
The present invention relates generally to three-level pulse-width modulation (PWM) modulators and specifically to the reduction of common-mode interference.
2. Related Art
In today's environment, class-D amplifiers are used to provide an integrated solution for applications such as powering audio devices. Class-D amplifiers have advantages in power consumption and size over more traditional analog amplifiers. Generally, they do not require bulky transformers or heat sinks, making them more suitable for integrated circuits.
In particular, the class-D amplifier unlike a traditional amplifier produces an output comprising a sequence of pulses. Typically, these pulses vary in width or in density in methods known as PWM or pulse density modulation (PDM). The average value of these pulses represents the instantaneous amplitude of the output signal. These pulses are also comprise unwanted high-frequency harmonics, which are typically removed by a low-pass filter.
FIG. 1 is a block diagram illustrating the typical architecture of class-D amplifier 100. The input signal is converted to pulses using modulator 102 which can be a pulse-width modulator or a pulse-density modulator. A common implementation of a pulse-width modulator uses a high-speed comparator to compare the input signal against a ramp or triangle wave. The modulated signal is then amplified by amplifier 104 and finally demodulated by low-pass filter 106. The demodulated signal can then be used, for example by speaker 108.
FIG. 2 illustrates a traditional class-D amplifier design using a binary PWM scheme. Pulse modulator 102 produces a PWM signal similar to the description above. The PWM signal drives two half-bridge circuits 206 and 208 with opposite polarities. Each half-bridge circuit performs the amplification. With relation to FIG. 1, amplifier 104 would comprise the two half-bridge circuits. In this example, inverter 202 is used to drive half-bridge circuit 206 whose output is shown as Houtp and buffer 204 is used to drive half-bridge circuit 208 whose output is shown as Houtn. The outputs of both half-bridge circuits result in a differential output signal that is filtered by low-pass filter 210 and drives load 212.
In power applications, low-pass filter 210 can be comprised of bulky and expensive passive inductors and capacitors. As a result, a recent trend in class-D audio amplifiers has been to advance from traditional binary, two-level PWM operation such as that described in FIG. 2 to a three-level PWM scheme. A three-level modulation scheme relaxes and potentially eliminates the need for external filtering between the amplifier and the load.
FIG. 3 illustrates a class-D amplifier design using a three-level modulation scheme. Modulation circuit 302 generates two outputs PWMp and PWMn, which drive two half-bridge circuits 308 and 310 through buffers 304 and 306, respectively. Unlike the two-level modulation scheme, PWMp and PWMn need not be of opposite polarity. Half-bridge circuit 308 produces output Houtp and half-bridge circuit 310 produces output Houtn. The result is a differential output signal of HoutDM=Houtp−Houtn, which optionally can be filtered by low-pass filter 312 and drives load 314. If low-pass filter 312 is used, due to the relaxed need, a less expensive low-pass filter could be used. It should be noted that even though modulation circuit 302 produces outputs with a combination of 4 potential states ([00], [01], [10], & [11]), due to the differential mode of operation, when PWMp and PWMn are the same ([00] or [11]) the resulting differential output signal HoutDM is zero. Hence, the output of modulation circuit 302 results in a net output of three differential output states.
FIG. 4 illustrates the outputs of the modulation circuits (or pulse modulators) and the resultant output states for both two-level and three-level modulation schemes. Table 400 shows the logic states for a two-level PWM scheme. The input to half-bridge circuit 206 is shown in the table as PWMp and the input to half-bridge circuit 208 is shown in the table as PWMn. Because the inputs are logically complementary, when PWMp is 1, PWMn is 0, and when PWMp is 0, PWMn is 1. The resultant logic is shown as PWMDM. PWMDM is related to HoutDM in that PWMDM represents the differential output logic of the pulse-width modulator and HoutDM is the actual differential output voltage of the amplifier. Typically, HoutDM∝PWMDM×(VDD−VSS). Also shown is a column for PWMCM, the common-mode output that will be discussed in greater detail later. Table 410 shows the logic states for a three-level PWM modulation scheme. The input to half-bridge circuit 308 is shown in the table as PWMp and the input to half-bridge circuit 310 is shown in the table as PWMn. Unlike the two-level modulation scheme, PWMp and PWMn are independent in the logical values they can take. The four different combinations are shown in table 410. As previously stated, the four input states result in only three unique differential output logic states (PWMDM=−1, 0, or +1). Hence, the design of FIG. 3 is a three-level modulation scheme.
Specifically to the two-level PWM case, FIG. 5 shows an example of signaling when VSS is grounded. The output of pulse modulator 102 is shown as PWMIN. In accordance with FIG. 2, the outputs of the each half-bridge circuit are shown as Houtp and Houtn. As described above, the differential output voltage HoutDM is the difference between the two half-bridge output voltages. The peak-to-peak differential voltage swing can be seen to be 2VDD. Alternatively, the common-mode output voltage, HoutCM, is defined as the average of the two half-bridge output voltages, HoutCM=½(Houtp+Houtn). Because each half-bridge circuit is driven by logically complementary signals, the common-mode signal is constant and has a magnitude of ½VDD.
While this type of PWM signaling is simple to implement, it has a fundamental drawback. Since the output levels Houtp and Houtn are always complimentary, there's always differential load current flowing. As illustrated when the amplifier input is zero, the differential output cannot be zero; it must take on the value of +VDD or −VDD. As a result, the amplifier must toggle between +VDD and −VDD with a 50% duty-cycle such that the low-frequency signal averages to a zero output. However, high-frequency switching currents are always present. This results in a large load current flowing even when there's no input. The large switching current results in greater loss in the load and amplifier, consequently reducing its power efficiency. In order to reduce these additional losses, a bulky, expensive output filter is usually required to isolate the speaker load from the high frequency switching current and to shunt any excess current to ground.
In contrast, FIG. 6 shows an example of signaling for the three-level PWM scheme in accordance with the circuit shown in FIG. 3. It should be noted that the primary difference of the three-level scheme compared to the two-level scheme is that each half-bridge driver is controlled independently. In particular, this allows Houtp and Houtn to be driven to the same level instead of always being complimentary. As can be seen at intervals 602, 604, 606, 608, 610, 612, and 614, the differential signal is now allowed to go to zero and the transitions are half as large as in the binary case. These improvements drastically lower the switching current and allow the output filter 310 to have significantly relaxed requirements or even be removed altogether.
FIG. 7 highlights the specific case when the input signal is zero. When the input signal is zero, the three-level PWM generator can cause Houtp and Houtn to take the same value producing a differential output HoutDM of zero. As mentioned before, a two level PWM scheme must have the differential output HoutDM switched between +VDD and −VDD, typically at the class-D amplifier's switching rate. Since there is no potential across the load in the three-level PWM case, there is no current flowing through the load, further underscoring the possibility of having a filter-free amplifier design.
However, the change to the three-level modulation scheme is accompanied with an increase in common-mode signaling. As seen in FIG. 5, a two-level modulation scheme yields a constant or direct current (DC) common-mode signal HoutCM, steady at ½VDD. On the contrary, as shown in FIG. 6, the three-level modulation scheme has a fluctuating common-mode signal HoutCM. While this common-mode signaling typically has little energy in the audio band and minimally impacts audio performance, it can have a lot of out-of-band energy that is concentrated into narrow bands that extend out to very high frequencies. These strong “spikes” of energy can couple into any circuitry that is placed in close proximity to the amplifier or speaker traces. This is a very common issue due to the miniaturization of electronics such as increasingly smaller laptops, cellular phones, and MP3 players.
It should be noted that the power and fidelity of the audio signal heard by the user are related primarily to the differential signal HoutDM. Any errors or non-idealities in the differential signal can result in increased distortion or noise in the speaker audio signal. On the other hand, while the common-mode signal HoutCM does not generally affect audio performance, it can result in electromagnetic interference (EMI) and electromagnetic compatibility (EMC) issues with neighboring circuitry.
As an example, FIG. 8 shows long speaker traces 806 and 808 between amplifier 802 and speaker load 804. Any potential external filter is omitted for clarity. Additionally, trace 810 is shown which is connected to some other circuitry that is in close proximity to the speaker traces. Any alternating current flowing through the speaker traces will induce a signal into the adjacent circuitry. This is a particularly significant problem with class-D amplifiers due to the large levels of current being sourced and sunk between the amplifier and the load.
Mathematically, expressions for the coupling between the speaker traces and the adjacent traces can be derived. From the previous definitions, Houtp and Houtn can be expressed in terms of their differential-mode and common-mode components, specifically, Houtp=+½HoutDM+HoutCM and Houtn=−½HoutDM+HoutCM. The voltage coupled from the speaker traces to adjacent node 816 is defined as Vemc. Define Gp(ƒ) as the coupling transfer function from positive speaker node 812 to adjacent node 816 and Gn(ƒ) as the coupling transfer function from negative speaker node 814 to adjacent node 816. Then the voltage coupled from the speaker nodes to adjacent node 816 is given by Vemc=Gp(ƒ)Houtp+Gn(ƒ)Houtn=Gp(ƒ)(½HoutDM+HoutCM)+Gn(ƒ)(−½HoutDM+HoutCM)=½[Gp(ƒ)−Gn(ƒ)]HoutDM[Gp(ƒ)+Gn(ƒ)]HoutCM.
Ideally, if the environment and distance between each speaker trace node and the offended circuitry can be maintained symmetrically (by such methods as careful layout or using twisted cabling), then the coupling transfer functions can be made substantially equal to one another, i.e., G(ƒ)=Gp(ƒ)=Gn(ƒ). Then, Vemc=2 G(ƒ)HoutCM. Thus the amount of voltage induced into the adjacent circuitry is ideally dependent only on the common-mode signaling.
Referring back to the common-mode waveform in FIG. 7, when the amplifier input signal is zero, the output common-mode signal is a square wave with a frequency equal to the class-D amplifier switching frequency. The spectrum of such a signal is shown in FIG. 9. The plot shows strong harmonics at odd multiples of the switching frequency extending out to very high frequencies. Even though the harmonics are outside of the audio band and do not affect the audio quality, these harmonics can easily couple into surrounding circuitry and degrade the impacted circuitry's performance. Thus it is important to reduce these harmonics in order to minimize EMI/EMC issues.
While the three-level PWM modulation scheme potentially allows filter-free differential operation, the accompanying common-mode signaling typically requires its own filtering to reduce the EMI/EMC issues. It is common practice to apply shielding or proper grounding of the end product's case in order to pass regulatory requirements. However, this shielding or grounding may not address interference within the enclosure. To resolve this interference, common-mode filtering via passive inductor-capacitor (LC) filtering is typically required to reduce common-mode harmonics to an acceptable level.
An alternative solution is to use spread-spectrum clocking to spread the out-of-band energy over a wider bandwidth so that the peaks are reduced. This essentially varies the clock's frequency over a band of values such that the class-D amplifier's switching frequency is spread out. The result is a spreading of the out-of-band energy and a reduction of the peaks. However, this also has an impact on the differential signaling. Empirical results have shown that spread-spectrum clocking can affect a class-D amplifier's linearity as well as dynamic range due to increased clock spurs and audio band noise. As a result, strict requirements must be placed on the spread-spectrum generator.
Thus there is a need in the industry for an inexpensive, compact solution that maintains the differential improvements of three-level PWM signaling while attenuating the common-mode harmonics without compromising the audio performance of the class-D amplifier.